(*DONT_TOUCH = "TRUE"*)
module single_pluse ( 
    input  clk,
    input  rst_n, 
    input  signal_in, 
    output pluse_out
    );

  reg delay_reg1;
  reg delay_reg2;
  
  always@(posedge clk or negedge rst_n)
  if(!rst_n)begin
    delay_reg1  <=  0;
    delay_reg2  <=  0;
  end
  else
    begin
      delay_reg1  <= signal_in  ;
      delay_reg2  <= delay_reg1 ;
    end
assign pluse_out= ~((!delay_reg1) | delay_reg2);

endmodule
